`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/04/18 21:59:36
// Design Name: 
// Module Name: SlaveMux
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module SlaveMux(
AXI4_Lite.Master s0,               //slave0
AXI4_Lite.Master s1,               //slave1
AXI4_Lite.Slave s, 
input logic m_sel_w,                    //根据该信号决定写哪个从机
input logic m_sel_r                     //根据该信号决定读哪个从机
    );
//slave --> master
always_comb
if(m_sel_w==0)
begin
    s.awready=s0.awready;
	s.wready=s0.wready;
	s.bvalid=s0.bvalid;
	s.bresp=s0.bresp;
end
else
begin
    s.awready=s1.awready;
	s.wready=s1.wready;
	s.bvalid=s1.bvalid;
	s.bresp=s1.bresp;
end
//master-->slave,to which slave depend on m_sel
always_comb
if(m_sel_w==0)
    s0.awvalid=s.awvalid;
else
    s0.awvalid=0;
always_comb
if(m_sel_w==0)
    s0.awaddr=s.awaddr;
else 
    s0.awaddr=0;
always_comb
if(m_sel_w==0)
    s0.wvalid=s.wvalid;
else
    s0.wvalid=0;
always_comb
if(m_sel_w==0)
begin
    s0.wdata=s.wdata;
	s0.wstrb=s.wstrb;
	s0.bready=s.bready;
end
else
begin
    s0.wdata=0;
	s0.wstrb=0;
	s0.bready=0;
end
//-->slave1
always_comb
if(m_sel_w==1)
    s1.awvalid=s.awvalid;
else
    s1.awvalid=0;
always_comb
if(m_sel_w==1)
    s1.awaddr=s.awaddr;
else 
    s1.awaddr=0;
always_comb
if(m_sel_w==1)
    s1.wvalid=s.wvalid;
else
    s1.wvalid=0;
always_comb
if(m_sel_w==1)
begin
    s1.wdata=s.wdata;
	s1.wstrb=s.wstrb;
	s1.bready=s.bready;
end
else
begin
    s1.wdata=0;
	s1.wstrb=0;
	s1.bready=0;
end
//*********************************************读***************************************
//master-->slave
always_comb
begin
   if(m_sel_r==0)
   begin
      s0.arvalid=s.arvalid;
	  s0.araddr=s.araddr;
	  s0.rready=s.rready;
	  s1.arvalid=0;
	  s1.araddr=0;
	  s1.rready=0;
   end
   else
   begin
      s1.arvalid=s.arvalid;
	  s1.araddr=s.araddr;
	  s1.rready=s.rready;
	  s0.arvalid=0;
	  s0.araddr=0;
	  s0.rready=0;
   end
end
//slave-->master
always_comb
begin
    if(m_sel_r==1'b0)             //slave0
    begin
      s.arready=s0.arready;
	  s.rvalid=s0.rvalid;
	  s.rdata=s0.rdata;
	  s.rresp=s0.rresp;
	end
    else
    begin
      s.arready=s1.arready;
	  s.rvalid=s1.rvalid;
	  s.rresp=s1.rresp;
	  s.rdata=s1.rdata;
    end
end
endmodule
